View AD7710ANZ_7219332.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

functional block diagram rev. g information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. a signal conditioning adc ad7710 features charge balancing adc 24 bits, no missing codes 0.0015% nonlinearity 2-channel programmable gain front end gains from 1 to 128 differential inputs low-pass filter with programmable filter cutoffs ability to read/write calibration coefficients bidirectional microcontroller serial interface internal/external reference option single- or dual-supply operation low power (25 mw typ) with power-down mode (7 mw typ) applications weigh scales thermocouples process control smart transmitters chromatography general description the ad7710 is a complete analog front end for low frequency measurement applications. the device accepts low level signals directly from a strain gage or transducer and outputs a serial digital word. it employs a sigma-delta conversion technique to realize up to 24 bits of no missing codes performance. the input signal is applied to a proprietary programmable gain front end based around an analog modulator. the modulator output is processed by an on-chip digital filter. the first notch of this digital filter can be programmed via the on-chip control register, allowing adjustment of the filter cutoff and settling time. the part features two differential analog inputs and a differen- tial reference input. typically, one of the channels will be used as the main channel with the second channel used as an auxil- iary input to measure a second voltage periodically. it can be operated from a single supply (by tying the v ss pin to agnd), provided that the input signals on the analog inputs are more positive than ?0 mv. by taking the v ss pin negative, the part can convert signals down to v ref on its inputs. the ad7710 thus performs all signal conditioning and conversion for a single- or dual-channel system. the ad7710 is ideal for use in smart, microcontroller based systems. input channel selection, gain settings, and signal polar- ity can be configured in software using the bidirectional serial port. the ad7710 contains self-calibration, system calibration, and background calibration options, and also allows the user to read and write the on-chip calibration registers. cmos construction ensures low power dissipation, and a soft- ware programmable power-down mode reduces the standby power consumption to only 7 mw typical. the part is available in a 24-lead, 0.3 inch-wide, plastic and hermetic dual-in-line package (dip) as well as a 24-lead small outline (soic) package. product highlights 1. the programmable gain front end allows the ad7710 to accept input signals directly from a strain gage or transducer, removing a considerable amount of signal conditioning. 2. the ad7710 is ideal for microcontroller or dsp processor applications with an on-chip control register that allows control over filter cutoff, input gain, channel selection, signal polarity, and calibration modes. 3. the ad7710 allows the user to read and write the on-chip calibration registers. this means that the microcontroller has much greater control over the calibration procedure. 4. no missing codes ensures true, usable, 23-bit dynamic range coupled with excellent 0.0015% accuracy. the effects of temperature drift are eliminated by on-chip self-calibration, which removes zero-scale and full-scale errors. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781/329-4700 www.analog.com fax: 781/326-8703 ? 2004 analog devices, inc. all rights reserved. clock generation serial interface control register output register charge-balancing a/d converter digital filter ad7710 m u x pga agnd dgnd mode sdata sclk a0 mclk out mclk in ain1(+) ain1(? ref in (? ref in (+) sync 4.5a a = 1 ?128 drdy tfs rfs ref out 2.5v reference av dd av dd 20a ain2(+) ain2(? i out v ss v bias av dd dv dd auto-zeroed - modulator
rev. g e2e parameter a, s versions 1 unit conditions/comments static performance no missing codes 24 bits min guaranteed by design. for filter notches 60 hz 22 bits min for filter notch = 100 hz 18 bits min for filter notch = 250 hz 15 bits min for filter notch = 500 hz 12 bits min for filter notch = 1 khz output noise tables i and ii depends on filter cutoffs and selected gain integral nonlinearity @ +25 c 0.0015 % of fsr max filter notches 60 hz t min to t max 0.003 % of fsr max typically 0.0003% positive full-scale error 2, 3 see note 4 excluding reference full-scale drift 5 1 v/ c typ excluding reference. for gains of 1, 2 0.3 v/ c typ excluding reference. for gains of 4, 8, 16, 32, 64, 128 unipolar offset error 2 see note 4 unipolar offset drift 5 0.5 v/ c typ for gains of 1, 2 0.25 v/ c typ for gains of 4, 8, 16, 32, 64, 128 bipolar zero error 2 see note 4 bipolar zero drift 5 0.5 v/ c typ for gains of 1, 2 0.25 v/ c typ for gains of 4, 8, 16, 32, 64, 128 gain drift 2 ppm/ c typ bipolar negative full-scale error 2 @ 25 c 0.003 % of fsr max excluding reference t min to t max 0.006 % of fsr max typically 0.0006% bipolar negative full-scale drift 5 1 v/ c typ excluding reference. for gains of 1, 2 0.3 v/ c typ excluding reference. for gains of 4, 8, 16, 32, 64, 128 analog inputs/reference inputs input common-mode rejection (cmr) 100 db min at dc and av dd = 5 v 90 db min at dc and av dd = 10 v common-mode voltage range 6 v ss to av dd v min to v max normal-mode 50 hz rejection 7 100 db min for filter notches of 10, 25, 50 hz, 0.02 f notch normal-mode 60 hz rejection 7 100 db min for filter notches of 10, 30, 60 hz, 0.02 f notch common-mode 50 hz rejection 7 150 db min for filter notches of 10, 25, 50 hz, 0.02 f notch common-mode 60 hz rejection 7 150 db min for filter notches of 10, 30, 60 hz, 0.02 f notch dc input leakage current 7 @ 25 c10 pa max t min to t max 1 na max sampling capacitance 7 20 pf max analog inputs 8 input voltage range 9 for normal operation. depends on gain selected 0 to +v ref 10 nom unipolar input range (b/u bit of control register = 1) v ref nom bipolar input range (b/u bit of control register = 0) input sampling rate, f s see table iii reference inputs ref in(+) e ref in(e) voltage 11 2.5 to 5 v min to v max for specified performance. part is functional with lower v ref voltages input sampling rate, f s f clk in /256 notes 1 temperature ranges are as follows: a version, e40 c to +85 c; s version, e55 c to +125 c. see also note 16. 2 applies after calibration at the temperature of interest. 3 positive full-scale error applies to both unipolar and bipolar input ranges. 4 these errors will be of the order of the output noise of the part as shown in table i after system calibration. these errors wi ll be 20 v typical after self-calibration or background calibration. 5 recalibration at any temperature or use of the background calibration mode will remove these drift errors. 6 this common-mode voltage range is allowed, provided that the input voltage on ain(+) and ain(e) does not exceed av dd + 30 mv and v ss e 30 mv. 7 these numbers are guaranteed by design and/or characterization. 8 the analog inputs present a very high impedance dynamic load that varies with clock frequency and input sample rate. the maximu m recommended source resistance depends on the selected gain (see tables iv and v). 9 the analog input voltage range on the ain1(+) and ain2(+) inputs is given here with respect to the voltage on the ain1(e) and a in2(e) inputs. the absolute voltage on the analog inputs should not go more positive than av dd + 30 mv or go more negative than v ss e 30 mv. 10 v ref = ref in(+) e ref in(e). 11 the reference input voltage range may be restricted by the input voltage range requirement on the v bias input. ad7710especifications (av dd = +5 v 5%; dv dd = +5 v 5%; v ss = 0 v or e5 v 5%; ref in(+) = +2.5 v; ref in(e) = agnd; mclk in = 10 mhz unless otherwise noted. all specifications t min to t max , unless otherwise noted.)
parameter a, s versions 1 unit conditions/comments reference output output voltage 2.5 v nom initial tolerance @ 25 c 1% max drift 20 ppm/ c typ output noise 30 v typ peak-peak noise 0.1 hz to 10 hz bandwidth line regulation (av dd )1 mv/v max load regulation 1.5 mv/ma max maximum load current 1 ma external current 1 ma max v bias input 12 input voltage range av dd e 0.85 v ref see v bias input section or av dd e 3.5 v max whichever is smaller: +5 v/e5 v or +10 v/0 v nominal av dd /v ss or av dd e 2.1 v max whichever is smaller; +5 v/0 v nominal av dd /v ss v ss + 0.85 v ref see v bias input section or v ss + 3 v min whichever is greater; +5 v/e5 v or +10 v/0 v nominal av dd /v ss or v ss + 2.1 v min whichever is greater; +5 v/0 v nominal av dd /v ss v bias rejection 65 to 85 db typ increasing with gain logic inputs input current 10 max all inputs except mclk in v inl , input low voltage 0.8 v max v inh , input high voltage 2.0 v min mclk in only v inl , input low voltage 0.8 v max v inh , input high voltage 3.5 v min logic outputs v ol , output low voltage 0.4 v max i sink = 1.6 ma v oh , output high voltage dv dd e 1 v min i source = 100 a floating state leakage current 10 a max floating state output capacitance 13 9 pf typ transducer burnout current 4.5 a nom initial tolerance @ 25 c 10 % typ drift 0.1 %/ c typ compensation current output current 20 a nom initial tolerance @ 25 c 4 a max drift 35 ppm/ c typ line regulation (av dd )2 0 na/v max av dd = +5 v load regulation 20 na/v max output compliance av dd e 2 v max system calibration positive full-scale calibration limit l4 (1.05 v ref )/gain v max gain is the selected pga gain (between 1 and 128) negative full-scale calibration limit l4 e(1.05 v ref )/gain v max gain is the selected pga gain (between 1 and 128) offset calibration limits 15 e(1.05 v ref )/gain v max gain is the selected pga gain (between 1 and 128) input span 15 0.8 v ref /gain v min gain is the selected pga gain (between 1 and 128) (2.1 v ref )/gain v max gain is the selected pga gain (between 1 and 128) notes 12 the ad7710 is tested with the following v bias voltages. with av dd = 5 v and v ss = 0 v, v bias = 2.5 v; with av dd = 10 v and v ss = 0 v, v bias = 5 v; and with av dd = 5 v and v ss = e5 v, v bias = 0 v. 13 guaranteed by design, not production tested. 14 after calibration, if the analog input exceeds positive full scale, the converter will output all 1s. if the analog input is le ss than negative full scale then the device will output all 0s. 15 these calibration and span limits apply, provided the absolute voltage on the analog inputs does not exceed av dd + 30 mv or go more negative than v ss e 30 mv. the offset calibration limit applies to both the unipolar zero point and the bipolar zero point. rev. g e3e ad7710
parameter a, s versions l unit conditions/comments power requirements power supply voltages av dd voltage 16 5 to 10 v nom 5% for specified performance dv dd voltage 17 5v nom 5% for specified performance av dd -v ss voltage 10.5 v max for specified performance power supply currents av dd current 4 ma max dv dd current 4.5 ma max v ss current 1.5 ma max v ss = e5 v power supply rejection 18 rejection w.r.t. agnd; assumes v bias is fixed positive supply (av dd and dv dd ) see note 19 db typ negative supply (v ss )90 db typ power dissipation normal mode 45 mw max av dd = dv dd = 5 v, v ss = 0 v; typically 25 mw 52.5 mw max av dd = dv dd = 5 v, v ss = e5 v; typically 30 mw standby (power-down) mode 15 mw max av dd = dv dd = 5 v, v ss = 0 v or e5 v; typically 7 mw notes 16 the ad7710 is specified with a 10 mhz clock for av dd voltages of +5 v 5%. it is specified with an 8 mhz clock for av dd voltages greater than 5.25 v and less than 10.5 v. operating with av dd voltages in the range 5.25 v to 10.5 v is only guaranteed over the 0 c to 70 c temperature range. 17 the 5% tolerance on the dv dd input is allowed provided that dv dd does not exceed av dd by more than 0.3 v. 18 measured at dc and applies in the selected passband. psrr at 50 hz will exceed 120 db with filter notches of 10 hz, 25 hz, or 5 0 hz. psrr at 60 hz will exceed 120 db with filter notches of 10 hz, 30 hz or 60 hz. 19 psrr depends on gain: gain of 1: 70 db typ; gain of 2: 75 db typ; gain of 4: 80 db typ; gains of 8 to 128: 85 db typ. these num bers can be improved (to 95 db typ) by deriving the v bias voltage (via zener diode or reference) from the av dd supply. specifications subject to change without notice. digital input voltage to dgnd . . . . . e0.3 v to av dd + 0.3 v digital output voltage to dgnd . . . . e0.3 v to dv dd + 0.3 v operating temperature range commercial (a version) . . . . . . . . . . . . . . . e40 c to +85 c extended (s version) . . . . . . . . . . . . . . . . . e55 c to +125 c storage temperature range . . . . . . . . . . . . . e65 c to +150 c lead temperature (soldering, 10 secs) . . . . . . . . . . . . . 300 c power dissipation (any package) to +75 c . . . . . . . . 450 mw derates above +75 c . . . . . . . . . . . . . . . . . . . . . . . . 6 mw/ c * stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of the specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. absolute maximum ratings * (t a = 25 c, unless otherwise noted.) av dd to dv dd . . . . . . . . . . . . . . . . . . . . . . . . e0.3 v to +12 v av dd to v ss . . . . . . . . . . . . . . . . . . . . . . . . . . . e0.3 v to +12 v av dd to agnd . . . . . . . . . . . . . . . . . . . . . . . e0.3 v to +12 v av dd to dgnd . . . . . . . . . . . . . . . . . . . . . . . e0.3 v to +12 v dv dd to agnd . . . . . . . . . . . . . . . . . . . . . . . . e0.3 v to +6 v dv dd to dgnd . . . . . . . . . . . . . . . . . . . . . . . . e0.3 v to +6 v v ss to agnd . . . . . . . . . . . . . . . . . . . . . . . . . . +0.3 v to e6 v v ss to dgnd . . . . . . . . . . . . . . . . . . . . . . . . . . +0.3 v to e6 v analog input voltage to agnd . . . . . . . . . . . . . . . . . . . . . . . . . v ss e 0.3 v to av dd + 0.3 v reference input voltage to agnd . . . . . . . . . . . . . . . . . . . . . . . . . v ss e 0.3 v to av dd + 0.3 v ref out to agnd . . . . . . . . . . . . . . . . . . . . e0.3 v to av dd ad7710especifications rev. g e4e caution esd (electrostatic discharge) sensitive device. electrostatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge without detection. although the ad7710 features proprietary esd protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality. warning! esd sensitive device
ad7710 rev. g e5e (dv dd = +5 v 5%; av dd = +5 v or +10 v 3 5%; v ss = 0 v or e5 v 10%; agnd = dgnd = 0 v; f clk in =10 mhz; input logic 0 = 0 v, logic 1 = dv dd , unless otherwise noted.) timing characteristics 1, 2 limit at t min , t max parameter (a, s versions) unit conditions/comments f clk in 4, 5 master clock frequency: crystal oscillator or externally 400 khz min supplied for specified performance 10 mhz max av dd = +5 v 5% 8 mhz max av dd = +5.25 v to +10.5 v t clk in lo 0.4 t clk in ns min master clock input low time. t clk in = 1/f clk in t clk in hi 0.4 t clk in ns min master clock input high time t r 6 50 ns max digital output rise time. typically 20 ns t f 6 50 ns max digital output fall time. typically 20 ns t 1 1000 ns min sync sc 2 drdy rfs s t drdy rfs t 2 c in rfs s t rfs t c in 2 rfs sc f c in 2 d t rfs d c in 2 sc f d d c in 2 c in 2 sc 1 c in 2 sc 1 tfs s t 1 tfs t 1 c in 2 tfs sc f d t 1 c in tfs sc f t 1 d sc s t 1 1 d sc t nts 1 1 1 2 s f 1 1 t d1 1 dd i dd 2 1 c in c in d1 stndy i t d1 c in 1 dd 2 i s 1 t f 1 2 rdrin id t 1 r 2 d1n c c n2 d1r c c r2 d1rr c c r2 d1rr c c r2 d1r c c r2 d1rr c c r2 d1rr c c r2 d1q c c q2 d1sq c 12 c q2 d1 nts 1 c 2 n di q crdi r sic
rev. g e6e ad7710 limit at t min , t max parameter (a, s versions) unit conditions/comments external clocking mode f sclk f clk in /5 mhz max serial clock input frequency t 20 0 ns min drdy rfs s t 21 drdy rfs t 22 2 c in rfs s t 2 rfs t 2 c in d t rfs d 2 1 sc f d d 2 c in 2 2 2 c in sc 2 2 c in sc 2 c in 1 sc f drdy 2 1 sc d t c in 1 1 rfs tfs sc f t 1 c in 2 rfs d t 2 tfs s t tfs t c in sc f tfs t 2 c in sc d sc s t d sc t nts t f 1 t 1 f t s in cnfirtin di nd sic sc c in dnd d dd d in1 nd c t sdt in1 i t rf t rf in rf in dd is 1 1 2 2 2 2 1 1 22 21 1 1 1 1 11 t i n s 11 12 1 d1 sync ss drdy rfs tfs n n ttt n f f ct rt
ad7710 rev. g e7e pin function descriptions pin mnemonic function 1 sclk serial clock. logic input/output, depending on the status of the mode pin. when mode is high, the device is in its self-clocking mode, and the sclk pin provides a serial clock output. this sclk becomes active when rfs tfs rfs tfs d sc t d1 2 c in c s d t c in c t c in cs c t t 1 c t c in c t i sync i d1 i d i in1 i c 1 t in1 t in1 i c 1 n in2 i c 2 1 in2 i c 2 n 11 ss n s t nd t in1 in2 ss 12 dd s 1 1 is i t is rf dd is rf ss rf rf in rf in i dd ss t dd ss rf t dd ss nd dd 1 1 rf in r i t rf in dd ss rf in rf in 1 rf in r i t rf in rf in rf in dd ss 1 rf t r t 2 t nd i 1 1 i t c c 2 t t 1 nd r c
rev. g e8e ad7710 pin mnemonic function 19 tfs t f s i tfs i tfs 2 rfs r f s i sc sdt rfs i sdt rfs 21 drdy t drdy drdy d1 22 sdt s d i d rfs drdy d sc tfs t 2 d dd d s d dd dd 2 dnd r d c t i n t t s 1 s 111 11 111 111 t fs 111 11 111 111 in in rf in 2 s i in in s t 111 111 1 in in s n fs t in in rf in s fs in in rf in n fs t in in rf in n in in ss c r i d1 t d1 fs c r t d1 i s i d1 t d1
ad7710 rev. g e9e control register (24 bits) a write to the device with the a0 input low writes data to the control register. a read to the device with the a0 input low acc esses the contents of the control register. the control register is 24 bits wide; 24 bits of data must be written to the register or the data will not be loaded. in other words, it is not possible to write just the first 12 bits of data into the control register. if more than 2 4 clock pulses are provided before tfs 2 s 2 s d2 d1 d 2 1 c d i fs11 fs1 fs fs fs fs fs fs fs fs2 fs1 fs s d2 d1 d n t t 1 sc t c t d2 d1 d t drdy f rf 1 s c t c t drdy t 1 1 s c t drdy 1 s c t c t drdy f rf 1 1 c t c i d1 t t i rf 11 r s c c c c t 2 t 2 11 1r fs c c c c t 2 t 2
rev. g e10e ad7710 pga gain g2 g1 g0 gain 000 1( default condition after the internal power-on reset) 001 2 010 4 011 8 100 16 101 32 110 64 111 128 channel selection ch channel 0 ain1 (default condition after the internal power-on reset) 1 ain2 power-down pd 0n ormal operation (default condition after the internal power-on reset) 1 power-down word length wl output word length 0 16-bit (default condition after internal power-on reset) 1 24-bit output compensation current io 0o ff (default condition after internal power-on reset) 1on burn-out current bo 0o ff (default condition after internal power-on reset) 1on bipolar/unipolar selection (both inputs) b/u 0 bipolar (default condition after internal power-on reset) 1 unipolar filter selection (fs11efs0) the on-chip digital filter provides a sinc 3 (or (sinx/x) 3 ) filter response. the 12 bits of data programmed into these bits deter- mine the filter cutoff frequency, the position of the first notch of the filter and the data rate for the part. in association with the gain selection, it also determines the output noise (and therefore the effective resolution) of the device. the first notch of the filter occurs at a frequency determined by the relationship: filter first notch frequency = (f clk in /512)/ code where code is the decimal equivalent of the code in bits fs0 to fs11 and is in the range 19 to 2,000. with the nominal f clk in of 10 mhz, this results in a first notch frequency range from 9.76 hz to 1.028 khz. to ensure correct operation of the ad7710, the value of the code loaded to these bits must be within this range. failure to do this will result in unspecified operation of the device. changing the filter notch frequency, as well as the selected gain, impacts resolution. tables i and ii and figure 2 show the effect of the filter notch frequency and gain on the effective resolution of the ad7710. the output data rate (or effective conversion time) for the device is equal to the frequency selected for the first notch of the filter. for example, if the first notch of the filter is selected at 50 hz, then a new word is available at a 50 hz rate or every 20 ms. if the first notch is at 1 khz, a new word is available every 1 ms. the settling time of the filter to a full-scale step input change is worst case 4 1/(output data rate). this settling time is to 100% of the final value. for example, with the first filter notch at 50 hz, the settling time of the filter to a full-scale step input change is 80 ms max. if the first notch is at 1 khz, the settling time of the filter to a full-scale input step is 4 ms max. this settling time can be reduced to 3 l/(output data rate) by syn- chronizing the step input change to a reset of the digital filter. in other words, if the step input takes place with sync i sync t 22
ad7710 rev. g e11e table i. output noise vs. gain and first notch frequency first notch of typical output rms noise ( v) filter and o/p e3 db data rate 1 frequency gain of 1 gain of 2 gain of 4 gain of 8 gain of 16 gain of 32 gain of 64 gain of 128 10 hz 2 2.62 hz 1.0 0.78 0.48 0.33 0.25 0.25 0.25 0.25 25 hz 2 6.55 hz 1.8 1.1 0.63 0.5 0.44 0.41 0.38 0.38 30 hz 2 7.86 hz 2.5 1.31 0.84 0.57 0.46 0.43 0.4 0.4 50 hz 2 13.1 hz 4.33 2.06 1.2 0.64 0.54 0.46 0.46 0.46 60 hz 2 15.72 hz 5.28 2.36 1.33 0.87 0.63 0.62 0.6 0.56 100 hz 3 26.2 hz 13 6.4 3.7 1.8 1.1 0.9 0.65 0.65 250 hz 3 65.5 hz 130 75 25 12 7.5 4 2.7 1.7 500 hz 3 131 hz 0.6 10 3 0.26 10 3 140 70 35 25 15 8 1 khz 3 262 hz 3.1 10 3 1.6 10 3 0.7 10 3 0.29 10 3 180 120 70 40 notes 1 the default condition (after the internal power-on reset) for the first notch of filter is 60 hz. 2 for these filter notch frequencies, the output rms noise is primarily dominated by device noise, and, as a result, is independe nt of the value of the reference voltage. therefore, increasing the reference voltage will give an increase in the effective resolution of the device (that is, the ratio of the rms noise to the input full scale is increased because the output rms noise remains constant as the input full scale increases). 3 for these filter notch frequencies, the output rms noise is dominated by quantization noise, and, as a result, is proportional to the value of the reference voltage. table ii. effective resolution vs. gain and first notch frequency first notch of effective resolution * (bits) filter and o/p e3 db data rate frequency gain of 1 gain of 2 gain of 4 gain of 8 gain of 16 gain of 32 gain of 64 gain of 128 10 hz 2.62 hz 22.5 21.5 21.5 21 20.5 19.5 18.5 17.5 25 hz 6.55 hz 21.5 21 21 20 19.5 18.5 17.5 16.5 30 hz 7.86 hz 21 21 20.5 20 19.5 18.5 17.5 16.5 50 hz 13.1 hz 20 20 20 19.5 19 18.5 17.5 16.5 60 hz 15.72 hz 20 20 20 19.5 19 18 17 16 100 hz 26.2 hz 18.5 18.5 18.5 18.5 18 17.5 17 16 250 hz 65.5 hz 15 15 15.5 15.5 15.5 15.5 15 14.5 500 hz 131 hz 13 13 13 13 13 12.5 12.5 12.5 1 khz 262 hz 10.5 10.5 11 11 11 10.5 10 10 note * effective resolution is defined as the magnitude of the output rms noise with respect to the input full scale (i.e., 2 v ref /gain). the above table applies for a v ref of 2.5 v and resolution numbers are rounded to the nearest 0.5 lsb. tables i and ii show the output rms noise for some typical notch and e3 db frequencies. the numbers given are for the bipolar input ranges with a v ref of 2.5 v. these numbers are typical and are generated with an analog input voltage of 0 v. the output noise from the part comes from two sources. first, there is the electrical noise in the semiconductor devices used in the implementation of the modulator (device noise). second, when the analog input signal is converted into the digital do- main, quantization noise is added. the device noise is at a low level and is largely independent of frequency. the quantization noise starts at an even lower level but rises rapidly with increas- ing frequency to become the dominant noise source. conse- quently, lower filter notch settings (below 60 hz approximately) tend to be device-noise dominated while higher notch settings are dominated by quantization noise. changing the filter notch and cutoff frequency in the quantization noise dominated region results in a more dramatic improvement in noise performance than it does in the device noise dominated region as shown in table i. furthermore, quantization noise is added after the pga, so effective resolution is independent of gain for the higher filter notch frequencies. meanwhile, device noise is added in the pga and, therefore, effective resolution suffers a little at high gains for lower notch frequencies. at the lower filter notch settings (below 60 hz), the no missing codes performance of the device is at the 24-bit level. at the higher settings, more codes will be missed until at the 1 khz notch setting; no missing codes performance is guaranteed only to the 12-bit level. however, because the effective reso- lution of the part is 10.5 bits for this filter notch setting, this no missing codes performance should be more than adequate for all applications. the effective resolution of the device is defined as the ratio of the output rms noise to the input full scale. this does not re- main constant with increasing gain or with increasing band- width. table ii is the same as table i except that the output is expressed in terms of effective resolution (the magnitude of the rms noise with respect to 2 v ref /gain, the input full scale). it is possible to do post filtering on the device to improve the output data rate for a given e3 db frequency and also to further reduce the output noise (see the digital filtering section).
rev. g e12e ad7710 1k 10 0.1 10 1k 10k 100 1 100 notch frequency e hz output noise e v gain of 16 gain of 32 gain of 64 gain of 128 figure 2b. output noise vs. gain and notch frequency (gains of 16 to 128) the basic connection diagram for the part is shown in figure 3. this figure shows the ad7710 in the external clocking mode with both the av dd and dv dd pins being driven from the ana- log 5 v supply. some applications have separate supplies for both av dd and dv dd , and in some cases, the analog supply exceeds the 5 v digital supply (see the power supplies and grounding section). ref in(+) ref out ain1(+) ain1(e) ain2(+) agnd dgnd mclk in mclk out mode sclk sdata drdy tfs rfs ref in(e) v bias sync a0 differential analog input analog ground digital ground data ready transmit (write) receive (read) serial data serial clock address input +5v ad7710 10 f 0.1 f 0.1 f analog +5v supply av dd dv dd v ss i out ain2(e) differential analog input figure 3. basic connection diagram figure 2 show information similar to that outlined in table i. in this plot, however, the output rms noise is shown for the ful l range of available cutoffs frequencies. the numbers given in these plots are typical values at 25 c. 10k 100 0.1 10 1k 10k 1k 10 1 100 gain of 1 gain of 2 gain of 4 gain of 8 notch frequency e hz output noise e v figure 2a. output noise vs. gain and notch frequency (gains of 1 to 8) circuit description the ad7710 is a sigma-delta a/d converter with on-chip digital filtering for measuring wide dynamic range, low frequency sig- nals in applications such as weigh scale, industrial control, or process control. it contains a sigma-delta (or charge-balancing) adc, a calibration microcontroller with on-chip static ram, a clock oscillator, a digital filter, and a bidirectional serial commu- nications port. the part contains two programmable gain differential analog input channels. the gain range is from 1 to 128 allowing the part to accept unipolar signals of 0 mv to 20 mv and 0 v to 2.5 v, or bipolar signals in the range of 20 mv to 2.5 v when the reference input voltage equals 2.5 v. the input signal to the selected analog input channel is continuously sampled at a rate determined by the frequency of the master clock, mclk in, and the selected gain (see table iii). a charge-balancing a/d converter (sigma-delta modulator) converts the sampled signal into a digital pulse train whose duty cycle contains the digital information. the programmable gain function on the analog input is also incorporated in this sigma-delta modulator with the input sampling frequency being modi fied to give the higher gains. a sinc 3 digital low-pass filter processes the output of the sigma-delta modulator and updates the output register at a rate determined by the first notch frequency of the filter. the output data can be read from the serial port randomly or periodically at any rate up to the output register update rate. the first notch of this digital filter (and therefore its e3 db frequency) can be programmed via an on-chip control register. the programmable range for this first notch frequency is 9.76 hz to 1.028 khz, giving a programmable range for the e3 db frequency of 2.58 hz to 269 hz.
ad7710 rev. g ?3 in operation, the analog signal sample is fed to the subtracter, along with the output of the 1-bit dac. the filtered difference signal is fed to the comparator, which samples the difference signal at a frequency many times that of the analog signal sam- pling frequency (oversampling). oversampling is fundamental to the operation of sigma-delta adcs. using the quantization noise formula for an adc, snr = ( 6.02 number of bits + 1.76) db , a 1-bit adc or comparator yields an snr of 7.78 db. the ad7710 samples the input signal at a frequency of 39 khz or greater (see table iii). as a result, the quantization noise is spread over a much wider frequency than that of the band of interest. the noise in the band of interest is reduced still further by analog filtering in the modulator loop, which shapes the quantization noise spectrum to move most of the noise energy to frequencies outside the bandwidth of interest. the noise perfor- mance is thus improved from this 1-bit level to the performance outlined in tables i and ii and in figures 2a and 2b. the output of the comparator provides the digital input for the 1-bit dac, so that the system functions as a negative feedback loop that tries to minimize the difference signal. the digital data that represents the analog input voltage is contained in the duty cycle of the pulse train appearing at the output of the compara- tor. it can be retrieved as a parallel binary data-word using a digital filter. sigma-delta adcs are generally described by the order of the analog low-pass filter. a simple example of a first-order sigma- delta adc is shown in figure 5. this contains only a first-order low-pass filter or integrator. it also illustrates the derivation of the alternative name for these devices, charge-balancing adcs. +fs ?s dac differential amplifier comparator integrator v in figure 5. basic charge-balancing adc the device consists of a differential amplifier (whose output is the difference between the analog input and the output of a 1-bit dac), an integrator and a comparator. the term charge balancing comes from the fact that this system is a negative feedback loop that tries to keep the net charge on the integrator capacitor at zero, by balancing charge injected by the input voltage with charge injected by the 1-bit dac. when the analog input is zero, the only contribution to the integrator output comes from the 1-bit dac. for the net charge on the integrator capacitor to be zero, the dac output must spend half its time at +fs and half its time at ?s. assuming ideal components, the duty cycle of the comparator will be 50%. when a positive analog input is applied, the output of the 1-bit dac must spend a larger proportion of the time at +fs, so the duty cycle of the comparator increases. when a negative input voltage is applied, the duty cycle decreases. the ad7710 uses a second-order sigma-delta modulator and a digital filter that provides a rolling average of the sampled out- put. after power-up, or if there is a step change in the input voltage, there is a settling time that must elapse before valid data is obtained. the ad7710 provides a number of calibration options that can be programmed via the on-chip control register. a calibration cycle may be initiated at any time by writing to this control register. the part can perform self-calibration using the on-chip calibration microcontroller and sram to store calibration parameters. other system components may also be included in the calibration loop to remove offset and gain errors in the input channel, using the system calibration mode. another option is a background calibration mode where the part continuously per- forms self-calibration and updates the calibration coefficients. once the part is in this mode, the user does not have to issue periodic calibration commands to the device or to recalibrate when there is a change in the ambient temperature or power supply voltage. the ad7710 gives the user access to the on-chip calibration registers, allowing the microprocessor to read the device calibra- tion coefficients and also to write its own calibration coefficients to the part from prestored values in e 2 prom. this gives the microprocessor much greater control over the ad7710? cali- bration procedure. it also means that the user can verify that the calibration is correct by comparing the coefficients after calibra- tion with prestored values in e 2 prom. the ad7710 can be operated in single-supply systems if the analog input voltage does not go more negative than ?0 mv. for larger bipolar signals, a v ss of ? v is required by the part. for battery operation, the ad7710 also offers a programmable standby mode that reduces idle power consumption to typically 7 mw. theory of operation the general block diagram of a sigma-delta adc is shown in figure 4. it contains the following elements: ? a sample-hold amplifier. ? a differential amplifier or subtracter. ? an analog low-pass filter. ? a 1-bit a/d converter (comparator). ? a 1-bit dac. ? a digital low-pass filter. s/h amp comparator digital data digital filter analog low-pass filter dac figure 4. general sigma-delta adc
rev. g e14e ad7710 input sample rate the modulator sample frequency for the device remains at f clk in /512 (19.5 khz @ f clk in = 10 mhz) regardless of the selected gain. however, gains greater than 1 are achieved by a combination of multiple input samples per modulator cycle and scaling the ratio of reference capacitor to input capacitor. as a result of the multiple sampling, the input sample rate of the device varies with the selected gain (see table iii). the effective input impedance is 1/ c f s where c is the input sampling capacitance and f s is the input sample rate. table iii. input sampling frequency vs. gain gain input sampling frequency (f s ) 1f clk in /256 (39 khz @ f clk in = 10 mhz) 22 f clk in /256 (78 khz @ f clk in = 10 mhz) 44 f clk in /256 (156 khz @ f clk in = 10 mhz) 88 f clk in /256 (312 khz @ f clk in = 10 mhz) 16 8 f clk in /256 (312 khz @ f clk in = 10 mhz) 32 8 f clk in /256 (312 khz @ f clk in = 10 mhz) 64 8 f clk in /256 (312 khz @ f clk in = 10 mhz) 128 8 f clk in /256 (312 khz @ f clk in = 10 mhz) digital filtering the ad7710 digital filter behaves like a similar analog filter, with a few minor differences. first, because digital filtering occurs after the a-to-d conversion process, it can remove noise injected during the conversion process. analog filtering cannot do this. on the other hand, analog filtering can remove noise super- imposed on the analog signal before it reaches the adc. digital filtering cannot do this, and noise peaks riding on signals near full scale have the potential to saturate the analog modulator and digital filter, even though the average value of the signal is within limits. to alleviate this problem, the ad7710 has over- range headroom built into the sigma-delta modulator and digital filter, which allows overrange excursions of 5% above the analog input range. if noise signals are larger than this, consideration should be given to analog input filtering, or to reducing the input channel voltage so that its full scale is half that of the analog input channel full scale. this will provide an overrange capability greater than 100% at the expense of reducing the dynamic range by 1 bit (50%). filter characteristics the cutoff frequency of the digital filter is determined by the value loaded to bits fs0 to fs11 in the control register. at the maximum clock frequency of 10 mhz, the minimum cutoff frequency of the filter is 2.58 hz while the maximum program- mable cutoff frequency is 269 hz. figure 6 shows the filter frequency response for a cutoff fre- quency of 2.62 hz, which corresponds to a first filter notch frequency of 10 hz. this is a (sinx/x) 3 response (also called sinc 3 ) that provides >100 db of 50 hz and 60 hz rejection. programming a different cutoff frequency via fs0efs11 does not alter the profile of the filter response, but changes the fre- quency of the notches as outlined in the control register section. gain e db frequency e hz 0 e240 070 10 20 30 40 50 60 e40 e80 e120 e160 e200 e20 e60 e100 e140 e180 e220 figure 6. frequency response of ad7710 filter since the ad7710 contains this on-chip, low-pass filtering, there is a settling time associated with step function inputs, and data from the output will be invalid after a step change until the settling time has elapsed. the settling time depends upon the notch frequency chosen for the filter. the output data rate equates to this filter notch frequency and the settling time of the filter to a full-scale step input that is four times the output data period. in applications using both input channels, the settling time of the filter must be allowed to elapse before data from the second channel is accessed. post filtering the on-chip modulator provides samples at a 19.5 khz output rate. the on-chip digital filter decimates these samples to pro- vide data at an output rate that corresponds to the programmed first notch frequency of the filter. because the output data rate exceeds the nyquist criterion, the output rate for a given band- width will satisfy most application requirements. however, there may be some applications that require a higher data rate for a given bandwidth and noise performance. applications that need a higher data rate will require some post filtering following the digital filter of the ad7710. for example, if the required bandwidth is 7.86 hz but the required update rate is 100 hz, the data can be taken from the ad7710 at the 100 hz rate, giving a e3 db bandwidth of 26.2 hz. post filtering can be applied to this to reduce the bandwidth and output noise to the 7.86 hz bandwidth level, while maintaining an output rate of 100 hz. post filtering can also to reduce the output noise from the device for bandwidths below 2.62 hz. at a gain of 128, the output rms noise is 250 nv. this is essentially device noise or white noise, and because the input is chopped, the noise has a flat frequency response. by reducing the bandwidth below 2.62 hz, the noise in the resultant pass band can be reduced. a reduction in bandwidth by a factor of 2 results in a 2 t
ad7710 rev. g e15e antialias considerations the digital filter does not provide any rejection at integer mul- tiples of the modulator sample frequency (n 19.5 khz, where n = 1, 2, 3 . . . ). this means that there are frequency bands f 3 db wide (f 3 db is cutoff frequency selected by fs0 to fs11), where noise passes unattenuated to the output. however, due to the ad7710?s high oversampling ratio, these bands occupy only a small fraction of the spectrum, and most broadband noise is filtered. in any case, because of the high oversampling ratio a simple rc, single-pole filter is generally sufficient to attenuate the signals in these bands on the analog input and thus provide adequate antialiasing filtering. if passive components are placed in front of the ad7710, ensure that the source impedance is low enough to keep from intro- ducing gain errors in the system. the dc input impedance for the ad7710 is over 1 g . the input appears as a dynamic load that varies with the clock frequency and with the selected gain (see figure 7). the input sample rate, as shown in table iii, determines the time allowed for the analog input capacitor c in to be charged. external impedances result in a longer charge time for this capacitor, which may result in gain errors being introduced on the analog inputs. table iv shows the allowable external resistance/capacitance values that do not introduce gain error to the 16-bit level, while table v shows the allowable external resistance/capacitance values that do not introduce gain error to the 20-bit level. both inputs of the differential input channels look into similar input circuitry. r int 7k typ c int 11.5pf typ v bias ain switching frequency depends on f clkin and selected gain high impedance >1g ad7710 figure 7. analog input impedance table iv. external series resistance that do not introduce 16-bit gain error external capacitance (pf) gain 0 50 100 500 1000 5000 1 184 k 45.3 k 27.1 k 7.3 k 4.1 k 1.1 k 2 88.6 k 22.1 k 13.2 k 3.6 k 2.0 k 560 4 41.4 k 10.6 k 6.3 k 1.7 k 970 270 8e128 17.6 k 4.8 k 2.9 k 790 440 120 table v. external series resistance that do not introduce 20-bit gain error external capacitance (pf) gain 0 50 100 500 1000 5000 1 145 k 34.5 k 20.4 k 5.2 k 2.8 k 700 2 70.5 k 16.9 k 10 k 2.5 k 1.4 k 350 4 31.8 k 8.0 k 4.8 k 1.2 k 670 170 8e128 13.4 k 3.6 k 2.2 k 550 300 80 the numbers in tables iv and v assume a full-scale change on the analog input. in any case, an error introduced due to longer charging times is a gain error that can be removed using the system calibration capabilities of the ad7710, provided that the resultant span is within the span limits of the system calibration techniques. analog input functions analog input ranges both analog inputs are differential, programmable gain input channels that can handle either unipolar or bipolar input signals. the common-mode range of these inputs is from v ss to av dd , provided that the absolute value of the analog input voltage lies between v ss e30 mv and av dd + 30 mv. the dc input leakage current is 10 pa maximum at 25 c ( 1 na over temperature). this results in a dc offset voltage developed across the source impedance. however, this dc offset effect can be compensated for by a combination of the differen- tial input capability of the part and its system calibration mode. burnout current the ain1(+) input of the ad7710 contains a 4.5 a current source that can be turned on/off via the control register. this current source can be used in checking that a transducer has not burned out or gone open circuit before attempting to take mea- surements on that channel. if the current is turned on and allowed to flow into the transducer and a measurement of the input voltage on the ain1 input is taken, it can indicate that the transducer has burned out or gone open circuit. for normal operation, this burnout current is turned off by writing a 0 to the bo bit in the control register. output compensation current the ad7710 also contains a feature that allows the user to implement cold junction compensation in thermocouple appli- cations. this can be achieved using the output compensation current from the i out pin of the device. once again, this current can be turned on/off via the control register. writing a 1 to the io bit of the control register enables this compensation current. the compensation current provides a 20 a constant current source that can be used in association with a thermistor or a diode to provide cold junction compensation. a common method of generating cold junction compensation is to use a temperature dependent current flowing through a fixed resistor to provide a voltage that is equal to the voltage developed across the cold junction at any temperature in the expected ambient range. in this case, the temperature coefficient of the compensa- tion current is so low compared with the temperature coefficient of the thermistor that it can be considered constant with tem- perature. the temperature variation is then provided by the variation of the thermistor?s resistance with temperature. normally, the cold junction compensation will be implemented by applying the compensation voltage to the second input chan- nel of the ad7710. periodic conversion of this channel gives the user a voltage that corresponds to the cold junction compensa- tion voltage. this can be used to implement cold junction com- pensation in software with the result from the thermocouple input being adjusted according to the result in the compensation channel. alternatively, the voltage can be subtracted from the input voltage in an analog fashion, thereby using only one chan- nel of the ad7710.
rev. g e16e ad7710 bipolar/unipolar inputs the two analog inputs on the ad7710 can accept either unipo- lar or bipolar input voltage ranges. bipolar or unipolar options are chosen by programming the b/u bit of the control register. this programs both channels for either type of operation. programming the part for either unipolar or bipolar operation does not change any of the input signal conditioning; it sim- ply changes the data output coding, using binary for unipolar inputs and offset binary for bipolar inputs. the input channels are differential and, as a result, the voltage to which the unipolar and bipolar signals are referenced is the voltage on the ain(e) input. for example, if ain(e) is 1.25 v and the ad7710 is configured for unipolar operation with a gain of 1 and a v ref of 2.5 v, the input voltage range on the ain(+) input is 1.25 v to 3.75 v. if ain(e) is 1.25 v and the ad7710 is configured for bipolar mode with a gain of 1 and a v ref of 2.5 v, the analog input range on the ain(+) input is e1.25 v to +3.75 v. reference input/output the ad7710 contains a temperature compensated 2.5 v refer- ence which has an initial tolerance of 1%. this reference volt- age is provided at the ref out pin, and it can be used as the reference voltage for the part by connecting the ref out pin to the ref in(+) pin. this ref out pin is a single-ended output, referenced to agnd, which is capable of providing up to 1 ma to an external load. in applications where ref out is connected to ref in(+), ref in(e) should be tied to agnd to provide the nominal 2.5 v reference for the ad7710. the refe rence inputs of the ad7710, ref in(+) and ref in(e) provide a differential reference input capability. the common- mode range for these differential inputs is from v ss to av dd . t he no minal differential voltage, v ref (ref in(+) e ref in (e)), is 2.5 v for specified operation, but the reference voltage can go to 5 v with no degradation in performance if the absolute value of ref in(+) and ref in(e) does not exceed its av dd and v ss limits, and the v bias input voltage range limits are obeyed. the part is also functional with v ref voltage down to 1 v but with degraded performance because the output noise will, in terms of lsb size, be larger. ref in(+) must always be greater than ref in(e) for correct operation of the ad7710. both reference inputs provide a high impedance, dynamic load similar to the analog inputs. the maximum dc input leakage cur- rent is 10 pa ( 1 na over temperature), and source resistance may result in gain errors on the part. the reference inputs look like the analog input (see figure 7). in this case, r int is 5 k typ and c int varies with gain. the input sample rate is f clk in /256 and does not vary with gain. for gains of 1 to 8, c int is 20 pf; for a gain of 16, it is 10 pf; for a gain of 32, it is 5 pf; for a gain of 64, it is 2.5 pf; and for a gain of 128, it is 1.25 pf. the digital filter of the ad7710 removes noise from the refer ence input just as it does with the analog input, and the same limita- tions apply regarding lack of noise rejection at integer multiples of the sampling frequency. the output noise performance out lined in tables i and ii assumes a clean reference. if the reference noise in the bandwidth of interest is excessive, it can degrade the performance of the ad7710. using the on-chip reference as the reference source for the part (that is, connecting ref out to ref in) results in degraded output noise perfor- mance from the ad7710 for portions of the noise table that are dominated by the device noise. the on-chip reference noise effect is eliminated in ratiometric applications where the refer- ence is used to provide the excitation voltage for the analog front end. the connection scheme, shown in figure 8, is recom- mended when using the on-chip reference. recommended refer- ence voltage sources for the ad7710 include the ad580 and ad680 2.5 v references. ref out ref in (+) ad7710 ref in (e) figure 8. ref out/ref in connection v bias input the v bias input determines at what voltage the internal analog circuitry is biased. it essentially provides the return path for analog currents flowing in the modulator and, as such, it should be driven from a low impedance point to minimize errors. for maximum internal headroom, the v bias voltage should be set halfway between av dd and v ss . the difference between av dd and (v bias + 0.85 v ref ) determines the amount of headroom the circuit has at the upper end, while the difference between v ss and (v bias e 0.85 v ref ) determines the amount of headroom the circuit has at the lower end. when choosing a v bias voltage, ensure that it stays within prescribed limits. for single 5 v operation, the selected v bias voltage must ensure that v bias 0.85 v ref does not exceed av dd or v ss or that the v bias voltage itself is greater than v ss + 2.1 v and less than av dd e 2.1 v. for single 10 v operation or dual 5 v opera- tion, the selected v bias voltage must ensure that v bias 0.85 v ref does not exceed av dd or v ss , or that the v bias voltage itself is greater than v ss + 3 v or less than av dd e3 v. for example, with av dd = 4.75 v, v ss = 0 v, and v ref = 2.5 v, the allowable range for the v bias voltage is 2.125 v to 2.625 v. with av dd = 9.5 v, v ss = 0 v, and v ref = 5 v, the range for v bias is 4.25 v to 5.25 v. with av dd = +4.75 v, v ss = e4.75 v, and v ref = +2.5 v, the v bias range is e2.625 v to +2.625 v. the v bias voltage does have an effect on the av dd power supply rejection performance of the ad7710. if the v bias voltage tracks the av dd supply, it improves the power supply rejection from the av dd supply line from 80 db to 95 db. using an external zener diode, connected between the av dd line and v bias , as the source for the v bias voltage gives the improvement in av dd power supply rejection performance.
ad7710 rev. g e17e using the ad7710 system design considerations the ad7710 operates differently from successive approxima- tion adcs or integrating adcs. because it samples the signal continuously, like a tracking adc, there is no need for a start convert command. the output register is updated at a rate determined by the first notch of the filter, and the output can be read at any time, either synchronously or asynchronously. clocking the ad7710 requires a master clock input, which may be an external ttl/cmos compatible clock signal applied to the mclk in pin with the mclk out pin left unconnected. alternatively, a crystal of the correct frequency can be con nected between mclk in and mclk out, in which case the clock circuit will function as a crystal-controlled oscillator. for lower clock frequencies, a ceramic resonator may be used instead of the crystal. for these lower frequency oscillators, external capacitors may be required on either the ceramic resonator or on the crystal. the input sampling frequency, the modulator sampling fre- quency, the e3 db frequency, the output update rate, and the calibration time are all directly related to the master clock fre- quency f clk in . reducing the master clock frequency by a factor of 2 will halve the above frequencies and update rate and will double the calibration time. the current drawn from the dv dd power supply is also directly related to f clk in . reducing f clk in by a factor of 2 will halve the dv dd current but will not affect the current drawn from the av dd power supply. system synchronization if multiple ad7710s are operated from a common master clock, they can be synchronized to update their output registers simul- taneously. a falling edge on the sync d1 d1 sync t d1 t sync d dd i d1 d dd d dd d1 t d1 d dd t d1 t d1 i d1 sync d1 d1 r c sync r c d dd sync s dc fc dc t d1 t t d1 d1 i d1 t d1 f t i 1 2 t d1 t t i drdy i drdy drdy t drdy sc i in in is rf t t rf t 1 d2 d1 d i
rev. g e18e ad7710 performed; the v ref node is then switched in and another conver- sion is performed. when the calibration sequence is complete, the calibration coefficients updated, and the filter resettled to the ana- log input voltage, the drdy t f i d1 s c s d1 s in s t i s 1 d2 d1 d t drdy 1 1 d2 d1 d drdy i t t 1 d2 d1 d t s r c s c s i in s 1 d2 d1 d t in in rf t in t drdy i c t d1 i rf t 1 1 d2 d1 d d1 t d2 d1 d d1 f 1 t i i t i c t t c t d2 d1 d s c fs c s d sc 1 s i rf s 1 r s c 1 in t s 1 r s c 1 1 in t s 1 r s c 1 in rf s 1 r c 1 1 s i rf s 1 r
ad7710 rev. g e19e span and offset limits whenever a system calibration mode is used, there are limits on the amount of offset and span that can be accommodated. the range of input span in both the unipolar and bipolar modes has a minimum value of 0.8 v ref /gain and a maximum value of 2.1 v ref /gain. the amount of offset that can be accommodated depends on whether the unipolar or bipolar mode is being used. this offset range is limited by the requirement that the positive full-scale calibration limit is 1.05 v ref /gain. therefore, the offset range plus the span range cannot exceed 1.05 v ref /gain. if the span is at its minimum (0.8 v ref /gain), the maximum the offset can be is (0.25 v ref /gain). in bipolar mode, the system offset calibration range is again restricted by the span range. the span range of the converter in bipolar mode is equidistant around the voltage used for the zero-scale point, thus the offset range plus half the span range cannot exceed (1.05 v ref / gai n ). if the span is set to 2 v ref / gain, the offset span cannot move more than (0.05 v ref / gain) before the endpoints of the transfer function exceed the input overrange limits (1.05 v ref /gain). if the span range is set to the minimum (0.4 v ref /gain), the maximum allowable offset range is (0.65 v ref /gain). power-up and calibration on power-up, the ad7710 performs an internal reset, which sets the contents of the control register to a known state. how- ever, to ensure correct calibration for the device, a calibration routine should be performed after power-up. the power dissipation and temperature drift of the ad7710 are low and no warm-up time is required before the initial calibration is performed. however, if an external reference is being used, this reference must have stabilized before calibration is initiated. drift considerations the ad7710 uses chopper stabilization techniques to minimize input offset drift. charge injection in the analog switches and dc leakage currents at the sampling node are the primary sources of offset voltage drift in the converter. the dc input leakage current is essentially independent of the selected gain. gain drift within the converter depends primarily upon the temperature tracking of the internal capacitors. it is not affected by leakage currents. measurement errors due to offset drift or gain drift can be elimi- nated at any time by recalibrating the converter or by operating the part in the background calibration mode. using the system calibration mode can also minimize offset and gain errors in the signal conditioning circuitry. integral and differential linearity errors are not significantly affected by temperature changes. power supplies and grounding because the analog inputs and reference input are differential, most of the voltages in the analog modulator are common-mode voltages. v bias provides the return path for most of the analog currents flowing in the analog modulator. as a result, the v bias input should be driven from a low impedance to minimize errors due to charging/discharging impedances on this line. when the internal reference is used as the reference source for the part, agnd is the ground return for this reference voltage. the analog and digital supplies to the ad7710 are independent and separately pinned out to minimize coupling between the analog and digital sections of the device. the digital filter will provide rejection of broadband noise on the power supplies, except at integer multiples of the modulator sampling frequency. the digital supply (dv dd ) must not exceed the analog positive supply (av dd ) by more than 0.3 v in normal operation. if sepa- rate analog and digital supplies are used, the recommended decoupling scheme is shown in figure 9. in systems where av dd = 5 v and dv dd = 5 v, it is recommended that av dd and dv dd are driven from the same 5 v supply, although each supply should be decoupled separately as shown in fig- ure 9. it is preferable that the common supply is the system?s analog 5 v supply. it is also important that power is applied to the ad7710 before signals at ref in, ain, or the logic input pins in order to avoid excessive current. if separate supplies are used for the ad7710 and the system digital circuitry, then the ad7710 should be powered up first. if it is not possible to guarantee this, then current limiting resistors should be placed in series with the logic inputs. ad7710 0.1 f 0.1 f 10 f analog supply digital +5v supply av dd dv dd figure 9. recommended decoupling scheme digital interface the ad7710?s serial communications port provides a flexible arrangement to allow easy interfacing to industry-standard microprocessors, microcontrollers, and digital signal processors. a serial read to the ad7710 can access data from the output register, the control register, or from the calibration registers. a serial write to the ad7710 can write data to the control register or the calibration registers. two different modes of operation are available, optimized for different types of interfaces where the ad7710 can act either as master in the system (it provides the serial clock) or as slave (an external serial clock can be provided to the ad7710). these two modes, labeled self-clocking mode and external clocking mode, are discussed in detail in the following sections. self-clocking mode the ad7710 is configured for its self-clocking mode by tying the mode pin high. in this mode, the ad7710 provides the serial clock signal used for the transfer of data to and from the ad7710. this self-clocking mode can be used with processors that allow an external device to clock their serial port including most digital signal processors and microcontrollers such as the 68hc11 and 68hc05. it also allows easy interfacing to serial- parallel conversion circuits in systems with parallel data commu- nication, allowing interfacing to 74xx299 universal shift regist ers without any additional decoding. in the case of shift registers, the serial clock line should have a pull-down resistor instead of the pull-up resistor shown in figure 10 and figure 11.
rev. g e20e ad7710 read operation data can be read from either the output register, the control register, or the calibration registers. a0 determines whether the data read accesses data from the control register or from the output/calibration registers. this a0 signal must remain valid for the duration of the serial read operation. with a0 high, data is accessed from either the output register or from the calibration registers. with a0 low, data is accessed from the control register. the function of the drdy drdy i 1 2 i drdy t drdy i drdy drdy d drdy i rfs drdy drdy f 1 d1 t d1 drdy d 2 f 1 d1 f sc drdy rfs rfs d1 s t sc s s sc c sc drdy drdy sc sdt t s sdt sc trstt rfs i i 1 drdy s s 2 f 1 sc d r
ad7710 rev. g e21e read operation as with self-clocking mode, data can be read from either the output register, the control register, or the calibration registers. a0 determines whether the data read accesses data from the control register or from the output/calibration registers. this a0 signal must remain valid for the duration of the serial read operation. with a0 high, data is accessed from either the output register or from the calibration registers. with a0 low, data is accessed from the control register. the function of the drdy drdy i 1 2 i drdy t drdy i drdy drdy d drdy i rfs drdy drdy d i drdy drdy 2 f 11 d1 t t tfs sc t d1 sc d d1 sc s sc s d1 s sc sc t f 11 sc c t d1 d i sc d1 sc t c1 c1 c11 c sdt i sc tfs i i 1 1 1 1 1 1 s s 1 f 11 sc cc r
rev. g e22e ad7710 figures 12a and 12b show timing diagrams for reading from the ad7710 in external clocking mode. in figure 12a, all the data is read from the ad7710 in one read operation. in figure 12b, the data is read from the ad7710 over a number of read operations. both read operations show a read from the ad7710?s output data register. a read from the control register or calibration registers is similar, but, in these cases, the drdy d 2 f 12 d1 rfs drdy rfs t sc rfs s t sc s drdy t drdy f 12 rfs t f 12 f 12 rfs rfs sc rfs sdt drdy d1 rfs d sc rfs it n1 rfs rfs sdt drdy sdt f 12 rfs i sc i sdt 2 2 s 2 s 2 trstt 2 i 22 2 21 2 2 drdy f 12 c d r trstt 2 2 s 1 it n 2 2 it n1 sdt sc i rfs i 2 i drdy 22 2 2 f 12 c d r rfs rr
ad7710 rev. g e23e write operation data can be written to either the control register or calibration registers. in either case, the write operation is not affected by the drdy drdy 2 f 1 d1 tfs t t d1 sc d d1 sc s sc s d1 f 1 d1 tfs t f 1 f 1 tfs d d1 sc tfs sc tfs d1 sc sc s d1 sc i sdt i i 2 s s 2 2 tfs (i) t 36 figure 13a. external clocking mode, control/calibration register write operation t 35 sclk (i) sdata (i) tfs s tn tn f cccr tfs r
rev. g e24e ad7710 simplifying the external clocking mode interface in many applications, the user may not need to write to the on-chip calibration registers. in this case, the serial interface to the ad7710 in external clocking mode can be simplified by connecting the tfs d1 f 1 t tfs rfs n d1 sdt sc tfs fr intrfc ins rfs f 1 s i tfs tfs rfs rfs tfs icrctricrrcssr intrfcin t d1 f 1 d1 f 1 d1 f 1 1 1 f 1 d1 drdy d drdy drdy r 2 drdy t rfs t t s s t d1 s f 1 2 d1 t s n ys rin rfs rrs rdr f its rin rfs i drdy cnfir nd initii c sri rt drdy rin rfs tfs i strt rd sri ffr f 1 f c r d1 f 1 t s s t d1 s i
ad7710 rev. g e25e reverse order of bits 3 start write data from accumulator to serial buffer bring tfs and a0 low load data from address to accumulator configure and initialize c/ p serial port bring rfs, tfs, and a0 high bring tfs and a0 high end figure 16. flowchart for single write operation to the ad7710 ad7710 to 8xc51 interface figure 17 shows an interface between the ad7710 and the 8xc51 microcontroller. the ad7710 is configured for external clock- ing mode, while the 8xc51 is configured in its mode 0 serial interface mode. the drdy d1 12 c1 drdy c1 t drdy int1 c1 1 1 11 12 1 c1 d1 sdt rfs tfs d drdy sync sc d dd f 1 d1 c1 i t ii c1 2 d1 t iii d1 t c1 s d1 s s d1 s c1 s t d1 t ii c1 c r d1 scn11 c 1 d i1 d i st s 1 rfs st 1 s 11 tfs st s 1 r1 s n r r r s r 12 drdy it n 1 r 1 n r drdy rd i r s it rd cr rfs cr c r f rd1 t r i f s rd 1 sf r rc r d c r rc 1c rc 2c rc c rc c rc c rc c rc c r d inc r i dc r1 d c r1 nd it f n nd st rfs fin s fin
rev. g e26e ad7710 table viii. 8xc51 code for writing to the ad7710 mov scon,#00000000b; configure 8051 for mode 0 operation and enable serial reception mov ie,#10010000b; enable transmit interrupt mov ip,#00010000b; prioritize the transmit interrupt setb 91h; bring tfs st tfs r1 s n r s r c sf i s it it i int rtin n i s r1 r1 fin i fin dc r1 d r1 c r inc r i rc r d s f s f c rc 1c rc 2c rc c rc c rc c rc c rc c cr cr 1 tfs sf s rti r s fin st 1 s tfs st s rti r i s d1 c11 i f 1 d1 c11 t d1 si c11 t drdy d1 c2 c11 drdy c11 t drdy irq c11 t c11 si is r d c11 si is t c11 c c 1 1 d1 c11 d1 sdt sc rfs tfs c is sc c1 c2 d c drdy sync c11 si ss d dd d dd f 1 d1 c11 i
ad7710 rev. g e27e clock generation serial interface control register output register charge-balancing a/d converter digital filter ad7710 m u x pga agnd dgnd mode sdata sclk a0 mclk out mclk i ain1(+) ain1(e) ref in(e) ref in(+) sync a = 1 e 128 drdy tfs rfs ain2(+) ain2(e) v ss v bias av dd dv dd 2.5v reference ref out analog 5v supply r r active gage dummy gage n auto-zeroed - modulator figure 19. strain-gage application with the ad7710 clock generation serial interface control register output register charge-balancing a/d converter auto-zeroed - modulator digital filter ad7710 m u x pga agnd dgnd mode sdata sclk a0 mclk out mclk in ain1(+) ain1(e) sync a = 1 e 128 drdy tfs rfs ain2(+) ain2(e) v ss v bias av dd dv dd 2.5v reference r r active gage dummy gage digital 5v supply analog supply excitation current ref in(+) r = v ref i excitation ref in(e) ref out figure 20. alternate scheme for generating ad7710 reference voltage applications figure 19 shows a strain gage interfaced directly to one of the analog input channels of the ad7710. the differential inputs to the ad7710 are connected directly to the bridge network of the strain gage. in the diagram shown, the on-chip reference of the ad7710 provides the voltage for the bridge network and also provides the reference voltage for the ad7710. an alternative scheme, outlined in figure 20, shows the analog positive supply voltage powering the bridge network and the ad7710, with the reference voltage for the ad7710 generated across a resistor that is placed in series with the bridge network. in this case, the value of the reference resistor is determined by the required reference voltage divided by the value of the excitation current. the on-chip pga allows the ad7710 to handle an analog input voltage range as low as 20 mv full scale. the differential inputs of the part allow this analog input range to have an absolute value anywhere between v ss and av dd .
rev. g e28e ad7710 outline dimensions 24-lead plastic dual in-line package [pdip] (n-24) dimensions shown in inches and (millimeters) 24 1 12 13 1.185 (30.01) 1.165 (29.59) 1.145 (29.08) 0.295 (7.49) 0.285 (7.24) 0.275 (6.99) 0.150 (3.81) 0.135 (3.43) 0.120 (3.05) 0.015 (0.38) 0.010 (0.25) 0.008 (0.20) 0.325 (8.26) 0.310 (7.87) 0.300 (7.62) seating plane 0.015 (0.38) min 0.180 (4.57) max 0.022 (0.56) 0.018 (0.46) 0.014 (0.36) 0.150 (3.81) 0.130 (3.30) 0.110 (2.79) 0.100 (2.54) bsc 0.060 (1.52) 0.050 (1.27) 0.045 (1.14) controlling dimensions are in inches; millimeter dimensions (in parentheses) are rounded-off inch equivalents for reference only and are not appropriate for use in design compliant to jedec standards mo-095ag 24-lead ceramic dual in-line package [cerdip] (q-24) dimensions shown in inches and (millimeters) 24 112 13 0.310 (7.87) 0.220 (5.59) pin 1 0.005 (0.13) min 0.098 (2.49) max 15 0 0.320 (8.13) 0.290 (7.37) 0.015 (0.38) 0.008 (0.20) seating plane 0.200 (5.08) max 1.280 (32.51) max 0.150 (3.81) min 0.200 (5.08) 0.125 (3.18) 0.023 (0.58) 0.014 (0.36) 0.100 (2.54) bsc 0.070 (1.78) 0.030 (0.76) 0.060 (1.52) 0.015 (0.38) controlling dimensions are in inches; millimeter dimensions (in parentheses) are rounded-off inch equivalents for reference only and are not appropriate for use in design
ad7710 rev. g e29e 24-lead standard small outline package [soic] wide body (r-24) dimensions shown in millimeters and (inches) controlling dimensions are in millimeters; inch dimensions (in parentheses) are rounded-off millimeter equivalents for reference only and are not appropriate for use in design compliant to jedec standards ms-013ad 8 0 0.75 (0.0295) 0.25 (0.0098) 45 1.27 (0.0500) 0.40 (0.0157) seating plane 0.30 (0.0118) 0.10 (0.0039) 2.65 (0.1043) 2.35 (0.0925) 1.27 (0.0500) bsc 24 13 12 1 10.65 (0.4193) 10.00 (0.3937) 7.60 (0.2992) 7.40 (0.2913) 15.60 (0.6142) 15.20 (0.5984) coplanarity 0.10 0.33 (0.0130) 0.20 (0.0079) 0.51 (0.0201) 0.31 (0.0122) outline dimensions
rev. g e30e ad7710 revision history location page 3/04?data sheet changed from rev. f to rev. g. changes to specifications note 16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 changes to ordering guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 deleted ad7710 to adsp-2105 interface section. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 deleted figure 19 and renumbered subsequent figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 changes to ad7710 to 68hc11 interface section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 updated outline dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
e31e 3/26/04 5:00 am_mb
c01168-0-3/04(g) ?2

▲Up To Search▲

Price & Availability of AD7710ANZ

	To Download AD7710ANZ Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .